Suppose we consider a classical chaotic electronic circuit,
possibly a Chua's oscillator, an RL-diode circuit, or a
switchmode power supply. The dynamic range of such a circuit will
be at most a factor of 
in voltage. This is comfortably
taken
care of by a digital representation having 32 bits. In fact, a
moderate number of bits (usually assumed to be
64 by the computing industry) is sufficient to represent the
greatest dynamic range of any practically observable quantity in
the universe. Thus, if we consider whether the standard analyses
of chaotic dynamics have applicability to digital machines, the
answer is clearly yes, particularly when such digital machines
incorporate small errors or changes in starting state which
classically can be thought of as giving rise to the
unpredictability of a chaotic system.
Thus an error of one bit in 32 represents the smallest error it is necessary to consider in the computer analysis of a classically chaotic electronic circuit. There is now a clear correspondence between the behaviour of a practical analogue chaotic circuit, and a computer simulation on an asynchronous digital parallel machine with arbitration errors introduced occasionally into the least significant bit of the state variable. The dynamics of the real circuit will be no less and no more predictable than the dynamics of the computer simulation; and neither real circuit nor simulation will do the same thing twice in a chaotic regime.
Thus it is clear that we can establish an arrangement and a problem for the parallel machine where chaotic dynamic analysis gives us as much information about the outcome as it does in the case of a real circuit. The generality of parallel machine arrangements may not be so well behaved, however. It is therefore necessary to generalise the state vector to an n-dimensional space each dimension of which is represented by 32 bits of the parallel machine's register states.
At this point the thrust of this paper becomes even more speculative. In a large fast parallel asynchronous machine, there will be a very large number of decompositions possible into 32 bit state variables. Let us hypothesize that we can do this in such a way that arbitration errors are only introduced as small errors in the state space trajectory of the point in machine space which describes the current state of the machine. In classical chaotic systems, there are constraints on the continuity and smoothness of the trajectory in phase space. Only local errors are introduced by added noise. It is clearly only a subset of our hypothetical parallel error-prone machines for which this is an accurate picture; nevertheless we consider that such a situation can be engineered.
Thus, suppose errors are only introduced into the LSBs of these variables. Now we run the machine forwards in time and consider what happens to such errors. It is clear, to these authors at least, that in the same sense that serial digital machines can compute trajectories having non-zero Lyapunov exponents, the asynchronous parallel machine may have some errors which then grow exponentially with well-defined rates. Considering an ensemble of such machines with a variety of starting errors, the average Lyapunov exponents displayed by the perturbed trajectories are not expected to be different from the Lyapunov exponent calculated for this system by a deterministic machine. This is for the same reason that the added noise in the starting point of an exponentially growing instability in the gate dynamics, as we have seen, does not affect the statistics of the gate settling times. Thus, if we are interested in the global quantities, such as average Lyapunov exponents, which are calculable for the system, the indeterminacy is of no consequence. It does however result in a richness of behaviour for the various trajectories within the ensemble, which is totally lacking in the deterministic machine. (Other errors may result in the catastrophic termination of the machine process; this is akin to a chaotic system containing traps [8] where the activity is rapidly captured by a stable fixed point after a long-lived chaotic transient.)
Such an indeterministic machine may then be described as a chaotic asynchronous digital parallel machine. This error-induced behaviour need not matter in certain applications which need the speed of such machines and may even be exploited to display the full richness of behaviours seen in the continuous-variable dynamical system that is being modelled.